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| 73S8009C Versatile Power Management and Smart Card Interface IC Simplifying System IntegrationTM DS_8009C_025 DATA SHEET January 2010 When power is supplied by VPC or VBAT , the 73S8009C is controlled by the ON_OFF pin in the manner of a "push-on/push-off" button action. The signals OFF_REQ and OFF_ACK provide handshaking and control of the power "off" function by the controller. A SPST momentary switch to ground connected to ON_OFF is all that is required for power control. Alternatively, the "off" state can be initiated from the host controller through OFF_ACK. When the 73S8009C is "off," the current is less than 1 A. When power is supplied via the VBUS pin, the 73S8009C is unconditionally in the "power-on" state regardless of the action of the ON/OFF switch or OFF_ACK signal. Power supply current operating from the VBUS power when VCC is off is less than 500 A to conform to USB "SUSPEND" requirements. APPLICATIONS * * * Handheld PINpad smart card readers for e-commerce, secure login, e-health, Gov't ID and loyalty Point of Sales & Transaction Terminals General Purpose Smart Card Readers DESCRIPTION The Teridian 73S8009C is a versatile power management and single smart card interface circuit that is ideally suited for smart card reader products that are battery and/or USB buspowered. In addition to its EMV 4.1 and ISO-7816-3 compliant smart card-to-host interface circuitry; it provides control, conversion, and regulation of power for a companion host processor circuit and power for the smart card. The 73S8009C can operate from a single 2.7 V to 6.5 V source supply, or a combination of battery power (4.0 V to 6.5 V) and USB power (4.4 V to 5.5 V). The 73S8009C supports 5 V, 3 V, and 1.8 V smart cards. The smart card signals for RST, CLK, IO, and auxiliary signals AUX1 and AUX2 are level-shifted to the selected VCC value. Although the host controller is required to handle the detailed signal timing for activation and deactivation under normal conditions, the 73S8009C blocks any spurious signals on CLK, RST and IO during power-up (as VCC rises) and power-down. The 73S8009C contains two handshaking signals for the controller: OFF indicates that a card is present, and RDY indicates that VCC is at an acceptable value. The 73S8009C will perform emergency deactivation upon card removal, voltage faults, or over-current events The power management circuitry of the 73S8009C allows operation from a wide range of voltages from multiple sources. VPC is converted by using an inductive, step-up power converter to the intermediate voltage, VP. VP is used by linear voltage regulators and switches to create the voltages VDD and as required, VCC. VDD is used by the 73S8009C and is also made available for the companion controller circuit or other external circuits. The two pins, VBAT and VBUS provide inputs from alternate power sources as required. An internal switch in the 73S8009C acts as a single-pole, double-throw switch that selects either VBAT or VBUS to be connected to VPC. When the voltage on VBUS is zero, VBAT is connected to VPC. When voltage is applied to VBUS, the switch will select VBUS as the source for power. Rev. 1.4 ADVANTAGES * Ideally suited to USB bus-powered applications Ideal for combo bus-powered and/or self-powered systems Automatic battery switchover in bus powered systems * Very low-power mode (sub-A) with push-button ON/OFF switch input with de-bounce Provides 3.3 V / 40 mA power to external circuitry (host processor or peripheral circuits) The inductor-based DC-DC converter provides higher current and efficiency than usual charge-pump capacitor-based converters: Ideal for battery-powered applications * * (c) 2010 Teridian Semiconductor Corporation 1 73S8009C Data Sheet FEATURES * Smart card Interface: * Complies with ISO-7816-3 and EMV 4.1 and derivative standards * A DC-DC Converter provides 1.8 V/3 V/5 V to the card from a wide range of external power supply inputs * Provides up to 65 mA to the card * ISO-7816-3 Card emergency deactivation sequencer * 2 voltage supervisors detect voltage drops on the VCC (card) and VDD (digital) power supplies * Card over-current detection 150 mA max. * 2 card detection inputs, 1 for either user polarity * Auxiliary I/O lines for synchronous and ISO-7816-12 USB card support * Card CLK clock frequency up to 20 MHz * 6 kV ESD and short circuit protection on the card interface * System Controller Interface: * 5 Signal images of the card signals (RSTIN, CLKIN, I/OUC, AUX1UC and AUX2UC) * 2 Inputs activate and select the card voltage (CMDVCC% and CMDVCC#) * 2 Outputs, interrupt to the system controller (OFF and RDY), to inform the system controller of the card presence / faults and status of the interface * 1 Chip Select input (CS - QFN32 only) * 2 Handshaking signals for proper shutdown sequencing of all output supply voltages (OFF_REQ, OFF_ACK) * ON/OFF Main System Switch: * Input for an SPST momentary switch to ground * DC-DC Converter: * Step-up converter DS_8009C_025 * Generates an intermediary voltage VP * Requires a single 10 H Inductor * System Power Supply requirements: * When using VBUS: Standard USB +5 input (range +4.4 V to 5.5 V) * When using VBAT : 4.0 V to 6.5 V * When using VPC: 2.7 V to 6.5 V * Automated detection of voltage presence Priority on VBUS over VBAT * Power Supply Output: * VDD supply output available to power up external circuitry: 3.3 V 0.3 V, 40 mA Industrial temperature range Small format QFN20 and QFN packages RoHS compliant (6/6) lead-free package * * * 2 Rev. 1.4 73S8009C Data Sheet FUNCTIONAL DIAGRAM CS 12 DS_8009C_025 TEST1 TEST2 10 [7] 30 [20] VDD 29 [19] VBAT VBUS 25 23 vref 15 [9] 24 [15] VOLTAGE REFERENCE VCC FAULT VPC FAULT VCC OK VCC = 5 VCC = 3 VP S2 S1 26 [16] bias currents VPC 27 [17] ON_OFF 4 [3] LIN SWITCH/LDO REGULATOR 17 [11] CMDVCC5 5 [4] CMDVCC3 OFF 32 [1] 8 GND 19 [13] CONTROL LOGIC POWER DOWN ON/OFF VCC RESET BUFFER 18 [12] RDY OFF_REQ OFF_ACK 11 9 RST RSTIN CLKIN 6 [5] 7 [6] 1.5MHz CLOCK BUFFER 16 [10] CLK 14 [8] PRES 13 PRES R-C OSC. I/OUC AUX1UC 1 [2] 2 3 22 [14] I/O SMART CARD I/O BUFFERS AND SIGNAL LOGIC 21 AUX1 20 AUX2UC AUX2 28 [18] GND Pin numbers reference to the QFN32 package [Pin numbers] reference to the QFN20 package Figure 1: 73S8009C Block Diagram Rev. 1.4 3 73S8009C Data Sheet DS_8009C_025 Table of Contents 1 2 Pinout ............................................................................................................................................. 6 Electrical Specifications.............................................................................................................. 10 2.1 Absolute Maximum Ratings ................................................................................................... 10 2.2 Recommended Operating Conditions .................................................................................... 11 2.3 Smart Card Interface Requirements ...................................................................................... 11 2.4 Digital Signals Characteristics ............................................................................................... 14 2.5 DC Characteristics ................................................................................................................ 15 2.6 Voltage / Temperature Fault Detection Circuits...................................................................... 15 2.7 Thermal Characteristics ........................................................................................................ 15 Applications Information ............................................................................................................. 16 3.1 Example 73S8009C Schematics ........................................................................................... 16 3.2 Power Supply and Converter ................................................................................................. 18 3.3 Interface Function - ON/OFF Modes...................................................................................... 18 3.4 System Controller Interface ................................................................................................... 20 3.5 Card Power Supply and Voltage Supervision......................................................................... 20 3.6 Activation and De-activation Sequence ................................................................................. 21 3.7 OFF and Fault Detection ....................................................................................................... 22 3.8 Chip Selection ....................................................................................................................... 23 3.9 I/O Circuitry and Timing......................................................................................................... 24 Equivalent Circuits ...................................................................................................................... 26 Mechanical Drawing .................................................................................................................... 30 Ordering Information ................................................................................................................... 32 Related Documentation ............................................................................................................... 32 Contact Information..................................................................................................................... 32 3 4 5 6 7 8 4 Rev. 1.4 DS_8009C_025 73S8009C Data Sheet Figures Figure 1: 73S8009C Block Diagram ......................................................................................................... 3 Figure 2: 73S8009C 32-Pin QFN Pinout .................................................................................................. 6 Figure 3: 73S8009C 20-Pin QFN Pinout .................................................................................................. 6 Figure 4: Typical 73S8009C Application Schematic ............................................................................... 17 Figure 5: 73S8009C Logical Block Diagram ........................................................................................... 19 Figure 6: Activation Sequence ............................................................................................................... 21 Figure 7: Deactivation Sequence ........................................................................................................... 22 Figure 8: OFF Activity ............................................................................................................................ 22 Figure 9: CS Timing Definitions.............................................................................................................. 23 Figure 10: I/O and I/OUC State Diagram ................................................................................................ 24 Figure 11: I/O - I/OUC Delays - Timing Diagram.................................................................................... 25 Figure 12: On_Off Pin ............................................................................................................................ 26 Figure 13: Open Drain type - OFF and RDY .......................................................................................... 26 Figure 14: Power Input/Output Circuit, VDD, LIN, VPC, VCC, VP ........................................................... 26 Figure 15: Smart Card CLK Driver Circuit .............................................................................................. 27 Figure 16: Smart Card RST Driver Circuit .............................................................................................. 27 Figure 17: Smart Card IO, AUX1, and AUX2 Interface Circuit................................................................. 28 Figure 18: Smart Card I/OUC, AUX1UC and AUX2UC Interface Circuit.................................................. 28 Figure 19: General Input Circuit ............................................................................................................. 29 Figure 20: OFF_REQ Interface Circuit ................................................................................................... 29 Figure 22: 20-Pin QFN Package Dimensions ......................................................................................... 30 Figure 22: 32-Pin QFN Package Dimensions ......................................................................................... 31 Tables Table 1: 73S8009C Pin Definitions .......................................................................................................... 7 Table 2: Absolute Maximum Device Ratings .......................................................................................... 10 Table 3: Recommended Operating Conditions ....................................................................................... 11 Table 4: DC Smart Card Interface Requirements ................................................................................... 11 Table 5: Digital Signals Characteristics .................................................................................................. 14 Table 6: DC Characteristics ................................................................................................................... 15 Table 7: Voltage / Temperature Fault Detection Circuits......................................................................... 15 Table 8: Thermal Characteristics ........................................................................................................... 15 Table 9: Order Numbers and Packaging Marks ...................................................................................... 32 Rev. 1.4 5 73S8009C Data Sheet DS_8009C_025 1 Pinout The 73S8009C is supplied as a 32-pin QFN package and as a 20-pin QFN package. TEST2 VBAT 25 GND GND VDD OFF 32 31 30 29 28 27 I/OUC AUX1UC AUX2UC CMDVCC5 CMDVCC3 RSTIN CLKIN RDY 1 2 3 4 5 6 7 8 10 11 12 13 14 15 TEST1 16 9 26 VPC LIN 24 23 22 ON_OFF VBUS I/O AUX1 AUX2 VCC RST GND TERIDIAN 73S8009C 21 20 19 18 17 OFF_REQ OFF_ACK PRES Figure 2: 73S8009C 32-Pin QFN Pinout TEST2 GND VDD PRES 20 19 18 17 OFF I/OUC CMDVCC% CMDVCC# RSTIN 16 VPC LIN CLK CS VP 1 2 3 4 5 15 14 ON_OFF I/O VCC RST GND TERIDIAN 73S8009C 13 12 11 PRES TEST1 VP Figure 3: 73S8009C 20-Pin QFN Pinout 6 CLKIN CLK 10 6 7 8 9 Rev. 1.4 DS_8009C_025 Table 1 describes the pin functions for the device. Table 1: 73S8009C Pin Definitions Pin Name Pin Pin Type (QFN32) (QFN20) Equivalent Circuit 73S8009C Data Sheet Description Card Interface I/O AUX1 AUX2 RST 22 21 20 18 14 N/A N/A 12 IO IO IO O Figure 17 Figure 17 Figure 17 Figure 16 Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC. AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. Card reset: provides reset (RST) signal to card. RST is the pass through signal on RSTIN. Internal control logic will hold RST low when card is not activated or VCC is too low. Card clock: provides clock signal (CLK) to card. CLK is the pass through of the signal on pin CLKIN. Internal control logic will hold CLK low when card is not activated or VCC is too low. Card Presence switch: active high indicates card is present. Should be tied to GND when not used, but it Includes a high-impedance pull-down current source. Card Presence switch: active low indicates card is present. Should be tied to VDD when not used, but it Includes a high-impedance pull-up current source. Card power supply - logically controlled by sequencer, output of LDO regulator. Requires an external 0.47 F low ESR filter capacitor to GND. Card ground. Clock signal source for the card clock. Factory test pin. This pin must be tied to GND in typical applications Factory test pin. This pin must be tied to GND in typical applications CLK 16 10 O Figure 15 PRES 14 8 I Figure 19 PRES 13 N/A I Figure 19 VCC 19 13 PSO Figure 14 GND CLKIN TEST1 TEST2 17 7 10 30 11 6 7 20 GND I - - - Figure 19 - - Miscellaneous Inputs and Outputs Power Supply and Ground VDD 29 19 PSO Figure 14 System interface supply voltage and supply voltage for companion controller circuitry. Requires a minimum of two 0.1 F capacitors to ground for proper decoupling. Rev. 1.4 7 73S8009C Data Sheet Pin Name VPC Pin Pin Type (QFN32) (QFN20) 26 16 PSI Equivalent Circuit Figure 14 DS_8009C_025 Description Power supply source for main voltage converter circuit. A 10 F and a 0.1 F ceramic capacitor must be connected to this pin. Alternate power source input, typically from two series cells, V > 4 V. Alternate power source input from USB connector or hub. VBAT VBUS LIN 25 23 27 N/A N/A 17 PSI Figure 14 Connection to 10 H inductor for internal step up converter. Note: inductor must be rated for 400 mA maximum peak current. Intermediate output of main converter circuit. Requires an external 4.7 F low ESR filter capacitor to GND Ground. VP 15 9 PSO Figure 14 GND 28,31 18 - Microcontroller Interface CS 12 N/A I Figure 19 When CS = 1, the control and signal pins are configured normally. When CS is set low, CMDVCC%, RSTIN, and CMDVCC#. are latched. I/OUC, AUX1UC, and AUX2UC are set to high-impedance pull-up mode and do not pass data to or from the smart card. Signals RDY and OFF are disabled to prevent a low output and the internal pull-up resistors are disconnected. Interrupt signal to the processor. Active Low Multi-function indicating fault conditions and card presence. Open drain output configuration - It includes an internal 20 k pull-up to VDD. Pull-up is disabled in Power down state and CS = 0 modes. System controller data I/O to/from the card. Includes a pull-up resistor to VDD. System controller auxiliary data I/O to/from the card. Includes a pull-up resistor to VDD. System controller auxiliary data I/O to/from the card. Includes a pull-up resistor to VDD. OFF 32 1 O Figure 13 I/OUC AUX1UC AUX2UC 1 2 3 2 N/A N/A IO IO IO Figure 18 Figure 18 Figure 18 8 Rev. 1.4 DS_8009C_025 Pin Name CMDVCC% CMDVCC# Pin Pin Type (QFN32) (QFN20) 4 5 3 4 I I Equivalent Circuit Figure 19 73S8009C Data Sheet Description Logic low on one or both of these pins will cause the LDO to ramp the Vcc supply to the smart card and smart card interface to the value described in the following table. CMDVCC% CMDVCC# Vcc Output Voltage 0 0 1 1 0 1 0 1 1.8 V 5.0 V 3.0 V LDO Off Note: See the description of the Card Power Supply for more detail on the operation of CMDVCC% and CMDVCC#. RSTIN RDY 6 8 5 N/A I Figure 19 Figure 13 Reset Input: This signal is the reset command to the card. Signal to controller indicating the 73S8009C is ready because VCC is above the required value after CMDVCC% and/or CMDVCC# is asserted low. A 20 k pull-up resistor to VDD is provided internally. Pull-up is disabled in Power down state and CS=0 modes. Power control pin. Connected to normally open SPST switch to ground. Closing switch for duration greater than de-bounce period will turn 73S8009C circuit "on." If 73S8009C is "on," closing switch will turn 73S8009C to "off" state after the de-bounce period and OFF_REQ/OFF_ACK handshake. Digital output. Request to the host system controller to turn the 73S8009C off. If ON_OFF switch is closed (to ground) for de-bounce duration and circuit is "on," OFF_REQ will go high (Request to turn OFF). Connected to OFF_ACK via 100 k internal resistor. Setting OFF_ACK high will power "off" all analog functions and disconnect the 73S8009C from VBAT or VPC. The pin has an internal 100 k resistor connection to OFF_REQ so that when not connected or no host interaction is required, the Acknowledge will be true and the circuit will turn "off" immediately with OFF_REQ. ON_OFF 24 15 I Figure 12 OFF_REQ 11 N/A O Figure 20 OFF_ACK 9 N/A I Figure 19 Rev. 1.4 9 73S8009C Data Sheet DS_8009C_025 2 Electrical Specifications This section provides the following: Absolute maximum ratings Recommended operating conditions Smart card interface requirements Digital signals characteristics Voltage / temperature fault detection circuits Thermal characteristics 2.1 Absolute Maximum Ratings Table 2 lists the maximum operating conditions for the 73S8009C. Permanent device damage may occur if absolute maximum ratings are exceeded. Exposure to the extremes of the absolute maximum rating for extended periods may affect device reliability. The smart card interface pins are protected against short circuits to VCC, ground, and each other. Table 2: Absolute Maximum Device Ratings Parameter Supply Voltage VBUS Supply Voltage VBAT Supply Voltage VPC VDD Input Voltage for Digital Inputs Storage Temperature Pin Voltage (except card interface) Pin Voltage (card interface) Pin Voltage, LIN pin ESD Tolerance - Card interface pins ESD Tolerance - Other pins Pin Current, except LIN Pin Current, LIN Rating -0.5 to 6.6 VDC -0.5 to 6.6 VDC -0.5 to 6.6 VDC -0.5 to 4.0 VDC -0.3 to (VDD +0.5) VDC -60 to 150C -0.3 to (VDD + 0.5) VDC -0.3 to (VCC + 0.3) VDC 0.3 to 6.5 VDC +/- 6 kV +/- 2 kV 200 mA + 500 mA in, -200 mA out Note: ESD testing on smart card pins is HBM condition, 3 pulses, each polarity referenced to ground. Note: Smart Card pins are protected against shorts between any combinations of Smart Card pins. 10 Rev. 1.4 DS_8009C_025 73S8009C Data Sheet 2.2 Recommended Operating Conditions Function operation should be restricted to the recommended operating conditions specified in Table 3. Table 3: Recommended Operating Conditions Parameter Supply voltage VPC Supply Voltage VBUS Supply Voltage VBAT Ambient operating temperature Rating 2.7 to 6.5 VDC 4.4 to 5.5 VDC 4.0 to 6.5 VDC -40 C to +85 C 2.3 Smart Card Interface Requirements Table 4 lists the 73S8009C Smart Card interface requirements. Table 4: DC Smart Card Interface Requirements Symbol Parameter Condition Card Power Supply (VCC) Regulator General Conditions: -40C < 85C, 2.7 V < VPC < 6.6 V Inactive mode Inactive mode ICC = 1 mA Active mode; ICC <65 mA; 5 V Active mode; ICC < 65 mA; 3 V Active mode; ICC < 40 mA; 1.8 V Active mode; single pulse of 100 mA for 2 s; 5 V, fixed load = 25 mA Active mode; single pulse of Card supply voltage VCC including ripple and noise 100 mA for 2 s; 3 V, fixed load = 25 mA Active mode; current pulses of 40nAs with peak |ICC | <200 mA, t <400 ns; 5 V Active mode; current pulses of 40nAs with peak |ICC | <200 mA, t <400 ns; 3 V Active mode; current pulses of 20nAs with peak |ICC | <100 mA, t <400 ns; 1.8 V VCCrip VCC ripple fRIPPLE = 20 kHz - 200 MHz ICCmax Card supply output Static load current, VCC>1.65 current Static load current, VCC>4.6 or 2.7 volts as selected ICCF ICC fault current Class A, B (5 V and 3 V) Class C (1.8 V) ISC Maximum current prior to Load current limit prior to Vcc shut-down shut-down Load current limit prior to Vcc shut-down for Vcc=1.8 V Min Nom Max Unit -0.1 -0.1 4.65 2.85 1.68 4.6 - - - - - - 0.1 0.4 5.25 3.15 1.92 5.25 V V V V V V 2.76 - 3.15 V 4.6 - 5.25 V 2.7 - 3.15 V 1.62 - 1.92 V - - - 75 55 80 60 - - - - 350 40 65 150 130 150 130 mV mA mA mA mA mA. mA Rev. 1.4 11 73S8009C Data Sheet VS Vrdy Vcc slew rate, rise and fall Vcc ready voltage (RDY = 1) RDY = 0 (VCC voltage supervisor threshold) External filter cap for VPC External filter cap for VP External filter capacitor (VCC to GND) VDD filter capacitor VPC supply current for Vcc=0 C = 0.5 F 5 V operation, Vcc rising 3 V operation, Vcc rising 1.8 V operation, Vcc rising VCC = 5 V 0.10 4.6 2.75 1.65 - 0.30 - - - - DS_8009C_025 0.70 - - - 4.6 V/s V V V V VCCF CVPC Cvp CF CVDD Ivpcoff CF should be ceramic with low ESR (<100m). 8.0 2.0 0.2 0.2 10.0 4.7 0.47 - 12.0 6.8 1.0 1.0 400 F F F F A Vpc=5 V, Vcc=0 V (off) 12 Rev. 1.4 DS_8009C_025 73S8009C Data Sheet Symbol Parameter Condition Min Nom Max Unit Interface Requirements - Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC, DP, DM. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, AUX2UC - VOH Output level, high (I/O, IOH =0 0.9 * VCC VCC+0.1 V AUX1, AUX2) - 0.75 VCC VOH Output level, high (I/OUC, IOH = -40 A VCC+0.1 V AUX1UC, AUX2UC) - IOH =0 0.9 VDD VDD+0.1 V - 0.75 VDD VOL Output level, low (I/O, VDD+0.1 V IOH = -40 A AUX1, AUX2) - - IOL=1 mA 0.15 *VCC V - - VOL Output level, low (I/OUC, IOL=1 mA 0.3 V AUX1UC, AUX2UC) - VIH Input level, high (I/O, 0.6 * VCC VCC+0.30 V AUX1, AUX2) - VIH Input level, high (I/OUC, 0.6 * VDD VDD+0.30 V AUX1UC, AUX2UC) - VIL Input level, low (I/O, -0.15 0.2 * VCC V AUX1, AUX2) - VIL Input level, low (I/OUC, -0.15 0.2 * VDD V AUX1UC, AUX2UC) - - VINACT Output voltage when IOL = 0 0.1 V outside of session - - IOL = 1 mA 0.3 V - - ILEAK Input leakage VIH = VCC 10 A - - IIL Input current, low (I/O, VIL = 0 0.65 mA AUX1, AUX2) - - IIL Input current, low (I/OUC, VIL = 0 0.7 mA AUX1UC, AUX2UC) - - ISHORTL Short circuit output For output low, shorted to 15 mA current VCC through 33 - - ISHORTH Short circuit output For output high, shorted to 15 mA current ground through 33 - - t R, t F Output rise time, fall For I/O, AUX1, AUX2, 100 ns times CL = 80pF, 10% to 90%. For I/OUC, AUX1UC, AUX2UC, CL=50Pf, 10% to 90%. - - tIR, tIF Input rise, fall times 1 s RPU Internal pull-up resistor Output stable for >200ns 8 11 14 k MHz FDMAX Maximum data rate - - 1 TFDIO Edge from master to 60 100 200 ns Delay, I/O to I/OUC, AUX1 to AUX1UC, AUX2 to slave, measured at 50% TRDIO - 15 - ns AUX2UC,I/OUC to I/O, AUX1UC to AUX1, AUX2UC to AUX2 (respectively falling edge to falling edge and rising edge to rising edge) CIN Input capacitance - - 10 pF Rev. 1.4 13 73S8009C Data Sheet DS_8009C_025 Symbol Parameter Condition Reset and Clock for card interface, RST, CLK VOH Output level, high IOH =-200 A VOL Output level, low IOL=200 A VINACT IRST_LIM ICLK_LIM t R, t F Output voltage when outside of session Output current limit, RST Output current limit, CLK Output rise time, fall time IOL = 0 Min 0.9 * VCC 0 - - - - - 45 Nom - - - - - - - - Max VCC 0.15 *VCC 0.1 30 70 12 100 55 Unit V V V mA mA ns ns % CL = 35pF for CLK, 10% to 90% CL = 200pF for RST, 10% to 90% CL =35pF, FCLK 20 MHz, CLKIN duty cycle is 48% to 52%. Duty cycle for CLK 2.4 Digital Signals Characteristics Table 5: Digital Signals Characteristics Table 5 lists the 73S8009C digital signals characteristics. Symbol Digital I/O (except for VIL VILOFFACK VIH VOL VOH ROUT RACK |I IL1 | tSL tDZ tIS tSI tID tDI Parameter Condition Min Nom Max Unit I/OUC, AUX1UC, AUX2UC; see Smart Card Interface Requirements for those specifications) - Input Low Voltage -0.3 0.8 V - 0.7 V Input low voltage for OFF_REQ pin = VDD -0.3 OFF_ACK pin - Input High Voltage 1.8 VDD + 0.3 V - Output Low Voltage IOL = 2 mA 0.45 V - Output High Voltage IOH = -1 mA VDD - 0.45 V Pull-up resistor; OFF, RDY 14 20 26 k Resistor between 70 100 130 k OFF_REQ and 0FF_ACK - Input Leakage Current GND < VIN < VDD - 5 A - - Time from CS goes high to 50 ns interface active - - Time from CS goes low to 50 ns interface inactive, Hi-Z - - Set-up time, control 50 ns signals to CS rising edge - Hold time, control signals - 50 ns from CS rising edge - - Set-up time, control 50 ns signals to CS fall - - Hold time, control signals 50 ns from CS fall 14 Rev. 1.4 DS_8009C_025 73S8009C Data Sheet 2.5 DC Characteristics Table 6 lists the DC characteristics. Table 6: DC Characteristics Symbol VDD IDDEXT Parameter VDD Supply Voltage VDD Current to External Load Vpc = 2.7V, VCC off, IDD = 0 Vpc = 3.3V, VCC off, IDD = 0 Vpc = 5.0V, VCC off, IDD = 0 OFF mode VDD =3.3 V Condition 2.7v < VPC < 6.5v, IVDDEXT < 40 mA. Min 3.0 - - - - - 3.5 0.5 Nom 3.3 - 1.7 1.1 0.7 0.01 3.9 1.0 370 Max 3.6 40 - - - 1 4.3 3 500 Unit V mA mA mA mA A V mA A IVPC Supply Current VBUSON VBUSIDIS VBUS detection threshold VBUS discharge current VBUSSTBY VBUS standby current 2.6 Voltage / Temperature Fault Detection Circuits Table 7 lists the voltage / temperature fault detection circuits. Table 7: Voltage / Temperature Fault Detection Circuits Symbol IVPmax ICCF ICCF1P8 Parameter VP over-current fault Card overcurrent fault Card overcurrent fault Condition Min - 80 60 Nom - - - Max 150 150 130 Unit mA mA mA VCC = 1.8 V 2.7 Thermal Characteristics Table 8 lists the thermal characteristics. Table 8: Thermal Characteristics Symbol Tj Parameter Junction temperature Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-case Condition Min - - - Nom - 70 6 Max 125 - - Unit ja jc C C/W C/W Rev. 1.4 15 73S8009C Data Sheet DS_8009C_025 3 Applications Information This section provides general usage information for the design and implementation of the 73S8009C. The documents listed in Related Documentation provide more detailed information. 3.1 Example 73S8009C Schematics Figure 4 shows a typical application schematic for the implementation of the 73S8009C with a main system switch. Note that minor changes may occur to the reference material from time to time and the reader is encouraged to contact Teridian for the latest information. 16 Rev. 1.4 DS_8009C_025 73S8009C Data Sheet VPC See NOTE 2 VDD VDD_supply_to_uC See NOTE 8 OFF_interrupt_to_uC See NOTE 7 10H See NOTE 3 VBAT C3 10F 25 26 27 28 29 30 31 32 See NOTE 1 VBUS VBAT VPC LIN GND VDD TEST2 GND OFF I/OUC_to/from_uC AUX1UC_to/from_uC AUX2UC_to/from_uC CMDVCC%_from_uC CMDVCC#_from_uC RSTIN_from_uC CLKIN_from_uC RDY_status_to_uC OFF_ACK_from_uC OFF_REQ_to_uC CS_from_uC 1 2 3 4 5 6 7 8 Pushbutton Switch ON/OFF VBUS I/O AUX1 AUX2 VCC RST GND 24 23 22 21 20 19 18 17 OFF_ACK TEST1 OFF_REQ CS PRES PRES VP CLK I/OUC AUX1UC AUX2UC CMDVCC% CMDVCC# RSTIN CLKIN RDY SW1 27pF C5 See NOTE 6 9 10 11 12 13 14 15 16 73S80009C 32 QFN See NOTE 5 0 27pF See NOTE 6 VDD See NOTE 4 R2 20K 4.7F C2 Card detection switch is normally closed C4 NOTES: 1) VBUS = 4.5V to 5.5V DC. 2) VPC = 2.7V to 6.5V DC (should only be used when VBAT and VBUS are unused) 3) VBAT = 4.0V to 6.5V DC. 4) Internal pull-up allows it to be left open if unused. 5) Resistor footpring is included in case some filtering is needed on CLK 6) Capacitors C4 and C5 are provisional and their footprints should be added for added noise rejection if necessary. 7) Inductor must be rated for 400 mA maximum peak current. 8) VDD - 3.3V, +/- 0.3V, 40mA max. Requires min two 0.1F caps to gnd) 0.47F, Low ESR (<100mohms) should be placed near the C1 SC connecter contact 10 9 SW-2 SW-1 C8 I/O VPP GND C4 CLK RST VCC 8 7 6 5 4 3 2 1 CLK track should be routed far from RST, I/O, C4 and C8 Smart Card Connector Figure 4: Typical 73S8009C Application Schematic Rev. 1.4 17 73S8009C Data Sheet DS_8009C_025 3.2 Power Supply and Converter The power supply and converter circuit takes power from any one of three sources; VPC, VBUS, and VBAT . VPC is specified to range from 2.7 to 6.5 volts and would typically be supplied by a single cell battery with a voltage range of 2.7 to approximately 3.1 volts. VPC is also appropriate for system supplies of 3.3 or 5 volts. VBUS is typically supplied by a connected USB cable and ranges in value from 4.5 to 5.5 volts (6.5 V maximum). VBAT is expected to be supplied from a battery of two series connected cells with a voltage value of 4.0 to 6.5 volts. VBAT and VBUS are connected to VPC by two FET switches configured as a SPDT switch (break-before-make). They will not be enabled at the same time. VBUS is automatically selected in lieu of VBAT when VBUS is present. If VPC is provided and VBAT or VBUS are also used, the source of VPC must be diode isolated from the VPC pin to prevent current flow from VBAT or VBUS into the VPC source. The power supplied to the VPC pin is up-converted to the voltage VP utilizing an inductive, step-up converter. A series power inductor (nominal value = 10 H) is connected from VPC to LIN, and a 10 F filter capacitor must be connected to VPC. VP requires a 4.7 F filter capacitor and will have a nominal value of 5.5 volts during normal operation. VP is used by the smartcard interface circuits (CLK, RST, IO, AUX1, and AUX2) and is the source of the regulated smart card supply VCC. VCC can be programmed for values of 5 V, 3 V, and 1.8 V. VDD is also produced from VP. VDD is used by the 73S8009C circuit for logic, input/output buffering, and analog functions as well as being capable of supplying up to 40 mA of current to external devices. Figure 2 shows the block diagram of the 73S8009C. 3.3 Power ON/OFF When no power is applied to the VBUS pin, a power ON/OFF function is provided such that the circuit will be inoperative during the "OFF" state, consuming minimum current from VPC and VBAT . If VBUS power is supplied, the functions of the ON/OFF switch and circuitry are overridden and the 73S8009C is in the "ON" state with VP and VDD available. Without VBUS applied, and in the OFF state, the circuit responds only to the ON_OFF pin. The ON_OFF pin shall be connected to a SPST switch to ground. If the circuit is OFF and the switch is closed for a de-bounce period of 50-100ms, the circuit shall go into the "ON" state wherein all functions are operating in normal fashion. If the circuit is in the "ON" state and the ON_OFF pin is connected to ground for a period greater than the de-bounce period, OFF_REQ will be asserted high and held. Typically, the OFF_REQ signal is presented to a host controller that will assert OFF_ACK high when it has completed all shutdown activities. When OFF_ACK is set high, the circuit will de-activate the smart card interface if required and turn off all analog functions and the VDD supply for the logic and companion circuits. The OFF_ACK pin is connected internally to OFF_REQ with a resistor such that if OFF_ACK is unconnected, the action of OFF_REQ will assert OFF_ACK high. In this configuration, the circuit shall go into the "OFF" state immediately upon OFF_REQ = 1. The default state upon application of power is the "OFF" state unless power is supplied to the VBUS supply. Note that at any time, the controller may assert OFF_ACK and the 73S8009C will go into the "OFF" state (when VBUS is not present.) If power is applied to both VBAT and VBUS, the circuit will automatically consume power from only the VBUS source. The circuit will be unconditionally "ON" when VBUS is applied. If the VBUS source is removed, the circuit will switchover to the VBAT input supply and remain in the "ON" state. The controller circuit firmware is required to assert OFF_ACK based on no activity or VBUS removal to reduce battery power consumption. When operating from VBUS, and not calling for VCC, the step-up converter becomes a simple switch connecting VBUS to VP in order to save power. This condition is appropriate for the USB "SUSPEND" state. The USB "SUSPEND" state requires the power supply current to be less than 500uA. In order to obtain and meet this low current limitation, the companion controller must be configured into a power-down condition using less than 20 A from VDD. Note: When using the VBUS input as the sole power source for an `always on' configuration (ON_OFF input not used), the OFF_ACK and ON_OFF inputs must be connected to ground. 18 Rev. 1.4 DS_8009C_025 73S8009C Data Sheet VBUS ON/OFF Debounce and Latch OFF_REQ 100K + - OFF_ACK VPC 10F 0.1F 10uH OFF ON LIN Linear/ DC - DC Converter 3.5VREF VP V1.8ThREF V3.0ThREF V5.0ThREF Delay Circuit VBAT RDY CS CMDVCC# CMDVCC% Analog Mux + VCC 0.47F VCC Regulator PRES PRES I/OUC RSTIN CLKIN AUX1UC AUX2UC 3.3V Regulator GND GND GND Card Supply/ Control Logic SHUTDOWN OFF Card I/O Buffer and Signal Logic I/O RST CLK AUX1 AUX2 VDD 0.1F 0.1F VP 4.7F Figure 5: 73S8009C Logical Block Diagram Rev. 1.4 19 73S8009C Data Sheet DS_8009C_025 3.4 System Controller Interface Four separate digital inputs and two outputs allow direct control of the card interface from the host: Pin CS: Chip select control. Pin CMDVCC# and/or CMDVCC%: When low, starts an activation sequence. Pin RSTIN: controls the card RST signal. Pin RDY: Indicates when smart card power supply is stable and ready. Pin OFF: Indicator of card presence and any card fault conditions. Interrupt output to the host: When the card is not activated, the OFF pin informs the host about the card presence only (Low = No card in the reader, high = card inserted). When CMDVCC (#/% signals) is/are set low (card activation sequence requested from the host), low level on OFF means a fault has been detected (e.g. card removal during card session, or voltage fault, or thermal / over-current fault) that automatically initiates a deactivation sequence. The smart card pass through signals are enabled when the RDY conditions are met. 3.5 Card Power Supply and Voltage Supervision The 73S8009C smart card interface IC incorporates an LDO voltage regulator for the card power supply, VCC (VP to VCC conversion uses an internal LDO). The voltage output is controlled by the digital input sequence of CMDVCC# and CMDVCC%. This regulator is able to provide 1.8V, 3V or 5V card voltage sourced from the VP power supply. Internal digital circuitry is also powered by the VP power supply (except for the ON/OFF circuitry which is powered from VPC). . A card deactivation sequence is forced upon fault detected by an overcurrent condition or card removal event. The voltage regulator can provide a card current of 65 mA in compliance with EMV 4.1 for 3-V and 5-V cards and 40 mA for 1.8 V cards. The signals CMDVCC# and CMDVCC% control the turn-on, output voltage value, and turn-off of VCC. When either signal is asserted low, VCC will ramp to the selected value or if both signals are asserted low (within 400ns of each other), VCC will ramp to 1.8V. These signals are edge triggered. If CMDVCC% is asserted low (to command VCC to be 5V) and at a much later time (greater than 2 s, typically), CMDVCC# is asserted low, it will be ignored (and vice versa.) At the assertion (low) of either or both CMDVCC (#/% signals), VCC will rise to the requested value. When VCC rises to an acceptable value, and stays above that value for approximately 20 s, RDY will be set high. Approximately 510 s after the fall of CMDVCC (#/%), the circuit will check the see if VCC is at or above the required minimum value (indicated by RDY=1) and if not, will begin an emergency deactivation sequence. During the 510 s time, card removal, or de-assertion of CMDVCC (#/%) shall also initiate an emergency deactivation sequence. The circuit provides over-current protection and limits Icc to 150 mA, maximum for self-protection. When an over-current condition is sensed, the circuit will invoke a de-activation sequence. 20 Rev. 1.4 DS_8009C_025 73S8009C Data Sheet 3.6 Activation and De-activation Sequence The host controller is fully responsible for the activation sequencing of the smart card signals CLK, RST, I/O, AUX1 and AUX2. All these signals are held low by the 73S8009C when the card is in the deactivated state. Upon card activation (the fall of CMDVCC (#/%)), all the signals are held low by the 73S8009C until RDY goes high. The host should set the signals RSTIN, I/OUC, CLKIN, AUX1UC and AUX2UC low prior to activating the card and allow RDY to go high before transitioning any of these signals. In order to initiate activation, the card must be present and OFF must be high. At t1 (500us), if RDY=0 or overcurrent, circuit will de-activate (safety feature) CMDVCC5 or CMDVCC3 VCC I/OUC I/O RDY RSTIN RST CLKIN CLK CLK=CLKIN if RDY=1 Ignored Ignored RST = RSTIN if RDY=1 Ignored I/O = I/OUC if RDY=1 t1 VCC valid I/O, AUX1, AUX2, CLK, RST are held LOW until RDY = 1 and CMDVCCx = 0 Figure 6: Activation Sequence Deactivation is initiated either by the system controller by setting both CMDVCC (#/%) high, or automatically in the event of hardware faults or assertion of the OFF_ACK signal. Hardware faults are over-current, under-voltage, and card extraction during the session. The host can manage the I/O signals, CLKIN, RSTIN, and CMDVCC (#/%) to create other de-activation sequences for non-emergency situations. The following steps show the deactivation sequence and the timing of the card control signals when the system controller sets the CMDVCC(x)B high: 1. 2. 3. 4. RST goes low at the end of time t1. De-assert CLK at the end of time t2. I/O goes low at the end of time t3. Exit reception mode. De-assert internal VCC_ON at the end of time t4. After a delay, VCC is de-asserted. Note: Since the 73S8009C does not control the waveshape of CLK (it is determined by the input form the host CLKIN), there is no guarantee that the duty cycle of the last CLK high pulse will conform to duty cycle requirements during an emergency deactivation. Rev. 1.4 21 73S8009C Data Sheet DS_8009C_025 CMDVCC RST CLK I/O VCC_ON VCC t1 t2 t3 t4 t5 Figure 7: Deactivation Sequence 3.7 OFF and Fault Detection There are two different cases that the system controller can monitor the OFF signal: to query regarding the card presence outside card sessions, or for fault detection during card sessions. Outside a card session: In this condition, CMDVCC (#/%) are always high, OFF is low if the card is not present, and high if the card is present. Because it is outside a card session, no fault detection can occur and it will not act upon the OFF signal. No deactivation is required during this time. During a card session: CMDVCC# and/or CMDVCC% is always low, and OFF falls low if the card is extracted or if any fault detection is detected. At the same time that OFF is set low, the sequencer starts the deactivation process and the host should stop all transitions on the signal lines. Figure 8 shows the timing diagram for the signals CMDVCC (#/%), PRES, and OFF during a card session and outside the card session. OFF is low by card extracted PRES OFF CMDVCC VCC outside card session within card session OFF is low by any fault within card session Figure 8: OFF Activity 22 Rev. 1.4 DS_8009C_025 73S8009C Data Sheet 3.8 Chip Selection The CS pin allows multiple circuits to operate in parallel, driven from the same host control bus. When CS is high, the pins RSTIN, CMDVCC%, CMDVCC# and CLKIN control the chip as described. The pins I/OUC, AUX1UC, and AUX2UC have 11 k pull-up resistors and operate to transfer data to the smart card via I/O, AUX1, and AUX2 when the smart card is activated. The signals OFF and RDY have 20 k pull-up resistors. When CS goes low, the states of the pins RSTIN, CMDVCC%, CMDVCC, and CLKIN are latched and held internally. The pull-up for pins I/OUC, AUX1UC, and AUX2UC become a very weak pull-up of approximately 3 microamperes. No transfer of data is possible between I/OUC, AUX1UC, AUX2UC and the smart-card signals I/O, AUX1, and AUX2. The signals OFF and RDY are set to high impedance and the internal pull-up resistors of 20 k are disconnected. With regard to de-activation, CS does not affect the operation of the fault sensing circuits and card sense input. tDZ CS OFF, I/OUC, AUX1UC, AUX2UC tSL HI-Z STATE HI-Z STATE FUNCTIONAL CONTROL SIGNALS tIS tSI tID tDI Figure 9: CS Timing Definitions Rev. 1.4 23 73S8009C Data Sheet DS_8009C_025 3.9 I/O Circuitry and Timing The states of the I/O, AUX1, and AUX2 pins are low after power on reset and they are in high when the activation sequencer turns on the I/O reception state. See the Activation and De-activation Sequence section for more details on when the I/O reception is enabled. The states of I/OUC, AUX1UC, and AUX2UC are high after power on reset. Within a card session and when the I/O reception state is turned on, the first I/O line on which a falling edge is detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected, then both I/O lines return to their neutral state. Figure 10 shows the state diagram of how the I/O and I/OUC lines are managed to become input or output. Neutral State No I/O reception Yes I/O & not I/OUC No Yes No I/OUC & not I/O Yes I/OUC in No I/OICC in No I/OUC I/O yes yes Figure 10: I/O and I/OUC State Diagram 24 Rev. 1.4 DS_8009C_025 The delay between the I/O signals is shown in Figure 11. 73S8009C Data Sheet I/O I/OUC tI/O_HL Delay from I/O to I/OUC: Delay from I/OUC to I/O: tI/O_LH tI/O_HL = 100ns tI/OUC_HL = 100ns tI/OUC_HL tI/OUC_LH tI/O_LH = 15ns tI/OUC_LH = 15ns Figure 11: I/O - I/OUC Delays - Timing Diagram Rev. 1.4 25 73S8009C Data Sheet DS_8009C_025 4 Equivalent Circuits This section provides illustrations of circuits equivalent to those described in the Pinout section. 24K PIN ESD VPC Figure 12: On_Off Pin VDD Output Disable 20K Data From circuit PIN ESD STRONG NFET Figure 13: Open Drain type - OFF and RDY PIN ESD To Internal circuits Figure 14: Power Input/Output Circuit, VDD, LIN, VPC, VCC, VP 26 Rev. 1.4 DS_8009C_025 VCC 73S8009C Data Sheet VERY STRONG PFET ESD From circuit ESD CLK PIN VERY STRONG NFET Figure 15: Smart Card CLK Driver Circuit VCC STRONG PFET ESD From circuit ESD RST PIN STRONG NFET Figure 16: Smart Card RST Driver Circuit Rev. 1.4 27 73S8009C Data Sheet VCC DS_8009C_025 ESD STRONG PFET 400ns DELAY RL=11K From circuit STRONG NFET IO PIN To circuit CMOS ESD Figure 17: Smart Card IO, AUX1, and AUX2 Interface Circuit VDD ESD STRONG PFET 400ns DELAY RL=11K From circuit STRONG NFET UC PIN To circuit CMOS ESD Figure 18: Smart Card I/OUC, AUX1UC and AUX2UC Interface Circuit 28 Rev. 1.4 DS_8009C_025 VDD 73S8009C Data Sheet Pull-up Disable VERY WEAK PFET ESD To circuit Pull-down Enable TTL PIN ESD VERY WEAK NFET Note: Pins CMDVCC%, CMDVCC#, CS have the pull-up enabled. Pins RSTIN, CLKIN, PRES, EXT_RST have the pull-down enabled. Pin OFF_ACK has a 100 k resistor connected to pin OFF_REQ internally. Figure 19: General Input Circuit VDD STRONG PFET ESD Output Disable PIN Data From circuit ESD STRONG NFET 100k ohm To OFF_ACK pad Notes: Strong PFET or NFET is approximately 100 Very strong PFET or NFET is approximately 50 Medium strength PFET is approximately 1 k Very weak PFET or NFET is approximately 1 M The diodes represent ESD protection devices that will conduct current if forward biased. Figure 20: OFF_REQ Interface Circuit Rev. 1.4 29 73S8009C Data Sheet DS_8009C_025 5 Mechanical Drawings 5.1 20-Pin QFN Mechanical Drawing 0.85 NOM / 0.90 MAX 0.02 NOM / 0.05 MAX 0.20 REF 4.0 20 2.0 1 2 4.0 2.0 SEATING PLANE TOP VIEW SIDE VIEW 0.18 / 0.30 2.50 / 2.70 1.25 / 1.35 0.20 MIN 0.18 / 0.30 2.50 / 2.70 2 K 1.25 / 1.35 1 0.35 / 0.45 20 PIN #1 ID R 0.20 19 0.20 MIN 0.50 BOTTOM VIEW Figure 21: 20-Pin QFN Package Dimensions 30 Rev. 1.4 DS_8009C_025 73S8009C Data Sheet 5.2 32-Pin QFN Mechanical Drawing 0.85 NOM./ 0.9MAX. 5 2.5 0.00 / 0.005 0.20 REF. 1 2 3 2.5 5 SEATING PLANE TOP VIEW SIDE VIEW 0.35 / 0.45 3.0 / 3.75 0.18 / 0.3 1.5 / 1.875 CHAMFERED 0.30 1 2 3 3.0 / 3.75 0.2 MIN. 0.35 / 0.45 Figure 22: 32-Pin QFN Package Dimensions 0.25 1.5 / 1.875 0.5 0.5 0.25 BOTTOM VIEW Rev. 1.4 31 73S8009C Data Sheet DS_8009C_025 6 Ordering Information Table 9 lists the order numbers and packaging marks used to identify 73S8009C products. Table 9: Order Numbers and Packaging Marks Part Description 73S8009C-20QFN 20-pin Lead-Free QFN 73S8009C-20QFN 20-pin Lead-Free QFN Tape / Reel 73S8009C-32QFN 32-pin Lead-Free QFN 73S8009C-32QFN 32-pin Lead-Free QFN Tape / Reel Order Number 73S8009C-20IM/F 73S8009C-20IMR/F 73S8009C-32IM/F 73S8009C-32IMR/F Packaging Mark S8009C S8009C 73S8009C 73S8009C 7 Related Documentation The following 73S8009C document is available from Teridian Semiconductor Corporation: 73S8009C Demo Board User's Guide 8 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 73S8009C, contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 Telephone: (714) 508-8800 FAX: (714) 508-8878 Email: scr.support@teridian.com For a complete list of worldwide sales offices, go to http://www.teridian.com. 32 Rev. 1.4 DS_8009C_025 73S8009C Data Sheet Revision History Revision 1.0 1.1 1.2 1.3 Date 2/15/2007 12/5/2007 1/21/2008 8/28/2009 First publication. Replaced 32 QFN punched with SAWN. Updated 32QFN package mark. Changed the dimension of the bottom view 32-pin QFN package. Added Pin Current, LIN to Table 2. Added Section 2.7, Thermal Characteristics. Added a note to the end of Section 3.6. Added Section 4, Equivalent Circuits. Added Section 7 Related Documentation and Section 8 Contact Information section. Formatted to new documentation style. Miscellaneous editorial changes. Changed the name of the "ON/OFF" pin to "ON_OFF" throughout the document. In Figure 1, corrected the name of the "IOUC" pin to "I/OUC". In Table 1, corrected the OFF_ACK name, pin number and type information. In Table 7, changed "IDDmax" to "IVPmax". At the end of Section 3.3, added a note about using VBUS input. In Section 3.5, deleted "A voltage supervisor checks the value of the voltage VCC" and added "and 40 mA for 1.8 V cards". Description 1.4 1/5/2010 Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. All other trademarks are the property of their respective owners. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. This Data Sheet is proprietary to Teridian Semiconductor Corporation (TSC) and sets forth design goals for the described product. The data sheet is subject to change. TSC assumes no obligation regarding future manufacture, unless agreed to in writing. If and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. Teridian Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability for applications assistance. Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com Rev. 1.4 33 |
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